In an endeavor to integrate green energy sources such as solar energy into the national grid, and provide cost effective electric car chargers and street lighting, a strong emphasis has been placed on providing an integrated circuit solution for electric car motor drivers, solar energy conversion, and other dc to grid ac conversion applications. This commonly requires voltage ranges of 600 V and above. Grid tolerant circuits for instance are tolerant to 700-1000V. These high voltage devices differ both functionally and structurally from low voltage devices since they need to deal with high voltages during normal operation without triggering as is discussed in greater detail below. High voltage devices have, for instance, been implemented as Lateral DMOS (LDMOS) (which is a self-aligned device implemented in a BiCMOS process) or as drain-extended MOS (DeMOS) (which is a non-self-aligned device implemented in a CMOS process). FIG. 1 shows a cross section through a typical NLDMOS-SCR 100, which broadly speaking comprises an LDMOS having one or more p+ regions 102 which are connected to the drain defined by n+ region 104 to provide for double injection of charge carriers. The n+ drain 104 is formed in an n-well or n-drift region 106, which in this case is formed in an n-epitaxial region 108 formed in or on a p-substrate 110. The device 100 further includes an n+ source 114 formed in a p-body or p-well 116, which is formed in the n-epi 108. In this embodiment the NLDMOS SCR 100 further includes a p+ backgate 118 formed in the p-well 116. A polysilicon gate 120, which is formed over a gate oxide 122 and a field oxide (FOX) 124, is provided between the drain contact 130 and source contact 128 and is located substantially equally spaced between the drain contact 130 and source contact 128. The region between the contacts defines the active region. For convenience during fabrication the p+ region 102 may be self aligned with the FOX region 124. However, even though devices such as the NLDMOS-SCR 100 are operable under normal operating conditions of between 300 and 1000V, the question is what happens to these devices under ESD conditions.
First impressions may suggest that, since very high voltage (VHV) and ultra high voltage (UHV) pins are already designed to accommodate high voltages during normal operation, that it is unnecessary to provide electrostatic discharge (ESD) protection for UHV pins. However, recent evaluations suggest that ESD protection is nevertheless required, especially system level protection in order to withstand the HBM (human body model) ESD pulse mode.
Thus the VHV and UHV devices have to be designed to tolerate the required dc levels during normal operation as well as the triggering voltage range during an ESD event. In the case of switching or noisy high voltage nodes this creates a problem. One solution has been to control the triggering voltage by dynamically coupling the control electrode of the clamp. For instance, as shown in FIG. 2, the gate of an LDSCR clamp 200 has in the past been connected to ground through a resistor 202. However, this can cause unpredictable triggering under different loads. Another form of dynamic coupling of the control electrode is that shown in FIG. 3, in which the gate is connected to a fixed voltage reference such as a zener diode 300 to control the control electrode, as shown in FIG. 3. This keeps the triggering voltage consistent under different loads. However, as is shown in FIG. 3, the Zener diode 300 in this example is tied between the switch pad 302 and the gate of the LDSCR 304. Thus the Zener 300 is tied to a high voltage and provides its voltage reference to the gate with respect to this high voltage. This solution is suitable for BiCMOS processes where the substrate is isolated with proper HV tolerance, but not for CMOS processes with their low breakdown voltage.
The present invention proposes, instead, a solution in which there is no dynamic coupling of the control electrode to a voltage reference, but one in which an SCR structure is internally triggered to enter conductivity modulation mode.